Such a communication switching element is already described in the international patent application No. PCT/EP88/00212 (P. Debuysscher 5). This known switch element includes a plurality of sets of memory circuits, the data inputs and outputs of each set of memory circuits being connected to a common output on the data write bus and to the output or transmitter circuits through a data read bus respectively. The input or receiver circuits are moreover coupled to a read and write control circuit which is provided in common for all the memory circuits and which is coupled to these memory circuits through an address bus. As a consequence only one memory circuit of a set may be selected at a time to enter data from a receiver circuit or to output data to the allocated output or transmitter circuit. This means that the same data cannot be written in two or more transmitter circuits, as may be for instance required when a point-to-multipoint connection has to be established. Also because the reading operation of the various memory circuits has to be performed in succession for these circuits this operation is relatively time consuming.